ATM CELL PROCESSOR

This module is a part of the ATM (Asynchronous Transfer Mode) protocol stack and implements the ATM (cell-level) layer. Functionality includes ATM cell delineation and synchronization; header error detection and correction; optional cell filtering. The module supports serial, 8-bit, 16-bit, and 32-bit data path widths. Optional UTOPIA interface is also available. The key benefits include:

Easy Integration

ATM Cell Processor is available as either Verilog or VHDL source code. The optional UTOPIA interface is available to aid the system integrator.

Easy Maintenance

The design has a modular structure. The well commented, self-documenting source code is easy to read and understand.

Reliability

The design has been extensively simulated and tested. The simulation test bench written in VHDL or Verilog is provided with the module. The implementation has been successfully tested with Xilinx FPGAs and CPLDs.

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