|
Home |
||||
| FRAME RELAY SCC | ||||
|
|
DATA SHEETThe Frame Relay Serial Communications Controller module implements the data link layer of the Frame Relay protocol. It is available in HDL source code written in either Verilog or VHDL. The following are the technical specifications: Supported StandardsThe Frame Relay SCC module is compliant with the following Frame Relay standards:
Hardware Description Language SupportThe design is offered as an HDL source code. The following languages are supported: VHDL (IEEE 1076-2008), Verilog HDL (IEEE 1364-2005).Simulation SupportAn HDL source code test bench accompanies the design to aid in simulation. Its functionality can be verified on any simulator of customer’s choice. The module has been tested on the following dual-language simulators: ModelSim, Aldec.Integration and Implementation SupportTo aid the integration of the design in a customer’s system, the following interfaces are provided:Generic FIFO Data Path, Wishbone SoC Bus, CoreConnect. The module’s compact and portable source code can be easily implemented in a variety of FPGA, CPLD, and ASIC architectures. The implementation has been successfully tested in programmable devices from the following vendors: Altera, Cypress, Xibnx. |
|||
|
||||