FRAME RELAY SCC

The Frame Relay Serial Communications Controller module implements the data link layer of the Frame Relay protocol. Its functionality includes frame synchronization, serial to parallel data conversion, zero bit extraction and insertion, Frame Check Sequence, frame length (min/max) and address fields integrity checking. It also offers an optional DLCI lookup. The core implements a generic FIFO data path interface. Optional Wishbone and CoreConnect interfaces are also available to aid with system integration. The key benefits include:

Easy Integration
Easy Maintenance
Reliability

The following is the Frame Relay Serial Communications Controller block diagram:

  ________________________________________
 |                   (hdlc_rx.vhd) ______ |       _____________
 |  ____________    __________    |      ||<-----|FF           |
-->|RXD (serial)|  | rcv data |   |(ext.)||----->|WE  external |
 | |   rcv line |->|processing|-->| fifo ||      |    rcv fifo |
-->|RCK   i/f   |  |          |<--| i/f  ||--/-->|RDAT  8 x 16 |
 |  ------------    ----------     ------ |  8    -------------
 |                        ^               |
  ------------------------|---------------
                          |     __________
                          |    |          |       _____________
                          |    | status   |<-----|CS           |
                          +--->| and      |<-----|RW  external |
                               | control  |----->|INT  cpu     |
                               | i/f      |<--/->|D    i/f     |
                          +--->|          |   8   -------------
                          |    |(ctrl.vhd)|
                          |     ----------
  ________________________|_______________
 |                        |        ______ |       _____________
 |  ____________    ______V___    |      ||<-----|EF           |
<--|TXD (serial)|  | xmt data |   |(ext.)||----->|RE  external |
 | |   xmt line |<-|processing|<--| fifo ||      |    xmt fifo |
-->|TCK   i/f   |  |          |<--| i/f  ||<--/--|TDAT  8 x 16 |
 |  ------------    ----------     ------ |   8   -------------
 |                   (hdlc_tx.vhd)        |
  ----------------------------------------

Easy Integration

The Frame Relay SCC is available as either Verilog or VHDL source code. The interfaces to two popular SoC (System on Chip) buses: Wishbone and CoreConnect are available to aid the system integrator.

Easy Maintenance

The design has a modular structure. The well commented, self-documenting source code is easy to read and understand. Extensive comments include even block diagrams (the block diagram above was copied from the source code).

Reliability

The design has been extensively simulated and tested. The simulation test bench written in VHDL or Verilog is provided with the module. The implementation has been successfully tested with Cypress, Xilinx, and Altera FPGAs.

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