TRILENT HDL MODULES

TRILENT Networks offers digital circuit building blocks written in VHDL or Verilog. These blocks reduce development workloads for hardware design engineers. Each block, also known as an IP (Intellectual Property) core, provides a specific, self-contained functionality that can be integrated into a larger system. Substantial savings over the in-house development can be realized by using these pre-designed blocks. Our designs are written in generic, fully synthesizeable VHDL and Verilog and include a simulation test bench.

Frame Relay SCC
Implements the data link layer of the Frame Relay protocol. Functionality includes: frame synchronization; serial to parallel data conversion; zero bit extraction and insertion; Frame Check Sequence; frame length and address fields integrity checking; optional DLCI lookup; generic FIFO data path interface.

ATM Cell Processor
This module is a part of the ATM (Asynchronous Transfer Mode) protocol stack. Implements the ATM (cell-level) layer. Functionality includes: ATM cell delineation and synchronization; header error detection and correction; optional cell filtering. The module supports serial, 8-bit, 16-bit, and 32-bit data path widths.

Gigabit Ethernet PCS
The Gigabit Ethernet PCS module implements the Physical Coding Sublayer (PCS) of the Gigabit Ethernet protocol stack, an important part of any Gigabit Ethernet implementation.

HDL Translator
This program translates VHDL source code into Verilog, preserving functionality, design hierarchy, and comments.