Implementing the Gigabit Ethernet Solution
The PCS module is an important part of any Gigabit Ethernet implementation – more so than would appear from a casual glance at the protocol stack diagram. This is because the implementation of the lower protocol layers (PMD and PMA) requires specialized technologies to support very high clock rates and a specific physical medium. These technologies are usually implemented by dedicated integrated circuits that are available off-the-shelf. The programmable logic or general-purpose ASICs cannot currently compete at these speeds. Therefore, there is no practical need for HDL modules to implement these layers.On the opposite side, the Media Access Control (MAC) layer specification has remained unchanged since the original Ethernet. Designs which implement this mature technology are widely available on the market. There is no need to "reinvent the wheel" by introducing another MAC design. This leaves the PCS as the only missing piece of the puzzle.
The block diagram below shows a complete Gigabit Ethernet implementation using the PCS module. The implementation includes:
- Transceiver chip appropriate to the medium used (copper or optical fiber). These are available from multiple vendors.
- Serializer-Deserializer chip, such as Vitesse VSC7123 or similar.
- FPGA or ASIC, implementing two IP cores: the PCS module and a third-party MAC core. An alternate implementation may use two separate FPGAs (ASICs), one for each core.
Implementing Fast Packet Processing
Two PCS modules can be used back-to-back in applications where fast processing or filtering of Gigabit Ethernet packets is required. An example application could be a hardware-based firewall or packet filter. This firewall is able to filter packets at a wire speed, making it a particularly useful protection against "Denial of Service" attacks.The hardware configuration consists of two complete Gigabit Ethernet physical interfaces connected as shown on a block diagram below. The two interfaces are connected at the GMII level through a packet processing module. The GMII interface includes a separate end-of-frame delimiter signal which makes packet synchronization at GMII easy to implement.
In our example application of an Internet firewall, the packet filtering module performs simple packet processing on both MAC and TCP/IP levels. It consists of the following functions:
- Packet Classifier examines the packet headers to detect TCP packets (frames). The non-TCP frames are not processed. They are rejected or passed through depending on the application. The end-of-frame GMII signal is used as a pointer to the beginning of each packet’s header.
- Packet Filter checks the TCP packet’s header against a set of firewall filtering rules. These can include a source or destination addresses or ports, SYN packet detection, etc. Non-compliant packets are rejected. If the packet was modified (rare in firewall applications), the TCP checksum must be recalculated.
- CRC Calculation must be done if the TCP packet was modified.
- Insertion of all the changes to the packet must be done before passing the packet on to the other GMII interface.
Fibre Channel Applications
The Gigabit Ethernet physical layer uses a slightly modified version of the Fibre Channel specification (ANSI X3.230-1994). Therefore, the PCS module can be easily implemented in a Fibre Channel application.Notice: The PCS specification (per IEEE Std 802.3) includes 8B/10B encoder/decoder which contains technology patented by the IBM. Implementers should obtain IBM license.
