Block Diagram
The following is the block diagram of the PCS module showing the
interface signals and internal functional blocks.
Functionality
The PCS functionality consists of the following functions:
- Transmit function continuously generates code-groups based upon the signals
of the GMII, sending them immediately to the TBI. The transmit process monitors
the Auto-Negotiation process flag to determine
whether to transmit data or reconfigure the link.
- Synchronization function continuously accepts code-groups via the TBI
receive interface and passes them to the Receive function. The synchronization process
sets the status flag to indicate whether the link is functioning dependably.
- Receive function continuously accepts code-groups and monitors these
code-groups and generates appropriate signal on the GMII.
- Auto-Negotiation function sets the xmit flag to inform the transmit
function to either transmit data or to reconfigure the link.
Interfaces
The PCS module communicates over two standard interfaces:
- GMII - Gigabit Media Independent Interface.
- TBI - Ten Bit Interface.
These interfaces connect with the upper and lower layers of the protocol stack, respectively.
When communicating over the GMII, the PCS uses an octet-wide, synchronous data
path, with packet delimiting being provided by separate control signals.
When communicating over the TBI, PCS uses a ten-bit wide, synchronous data path.
Packet delimiting is provided by special 10-bit code groups in the data stream.
Supported Standards
The Gigabit Ethernet PCS module is compliant with the following standards:
- IEEE Std 802.3 (1998) CSMA/CD access method and physical layer specifications.
- ANSI Technical Report TR/X3.18 (1997) Fiber Channel - 10 bit Interface.
HDL Language Support
The design is offered as an HDL source code. The following languages are supported:
Simulation Support
An HDL source code test bench accompanies the design to aid in simulation. Its functionality
can be verified on any simulator of the customer’s choice.
The module has been tested on the following dual-language simulators:
Implementation Support
The module’s source code is fairly complex. Technical support offers
assistance with its implementation. The implementation has been successfully tested
in Xilinx Virtex II FPGAs.
