HDL TRANSLATOR


 

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DATA SHEET

HDL Translator converts a VHDL design into an equivalent design in Verilog HDL. The following are the technical specifications.


Supported Standards

The HDL source code translation is based on the following standards:
  • IEEE Std 1076-1987 - IEEE Standard VHDL Language Reference Manual
  • IEEE Std 1076/INT-1991 - IEEE Standards Interpretations: Standard VHDL Language Reference Manual
  • IEEE Std 1164-1993 - IEEE Standard Multi-Value Logic System for VHDL Model Interoperability
  • IEEE Std 1364-1995 - Verilog Hardware Description Language Reference Manual

Assumptions

For simplification, the following assumptions were made about the input VHDL code to be translated:
  • VHDL syntax is correct (i.e. the code compiles w/o errors)
  • VHDL code is synthesizeable
  • One architecture per entity

Systems Supported

HDL Translator is implemented as a command line utility. It is compatible with both Windows and Unix systems. It was tested on:
  • Windows 98/Me/NT/2000/XP/2003
  • Linux
  • BSD Unix
  • Sun Solaris


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