How fast is the HDL Translator?
Quite fast. On reasonably fast computer, it would translate 6,000 lines of VHDL code in
under a minute.
Will it translate 100% of VHDL code?
No VHDL to Verilog converter on the market translates all possible code, as far as we know.
It would be impractical to do so. 80% of development effort would be used on language intricacies nobody
uses. That would price the product out of the market. Our HDL Translator takes a practical approach.
It will translate 100% of synthesizeable code. It will translate most behavioral code, including
the constructs most frequently used in test bench design. The part of source code it cannot translate
will be commented out, for subsequent manual translation. The remainder of the code will be translated.
In a hypothetical 6,000 line source code, five to ten lines may be commented out
(left un-translated).
It is obvious that in this example the HDL Translator has saved several man-weeks of work.
The remaining 10 lines can be converted by hand usually within an hour.
How important is preserving comments?
We think it is very important. In a complex code, comments are crucial to the maintenance of the
design because they tell you the "why".
For example, consider a part of a design which delays clock by three cycles.
That much is obvious from the code. But why? In any non-trivial code the
answer may not be easy without comments.
The HDL Translator preserves all comments, and somewhat preserves formatting. As an unexpected byproduct,
it also preserves
coding style. Often you can tell who wrote the original code.
Can the HDL Translator convert from Verilog to VHDL?
Not yet. This feature is under development, so stay tuned.
