HDL TRANSLATOR

The Trilent HDL Translator converts a VHDL design into an equivalent design in Verilog® hardware description language. The translation is performed on the source code level maintaining functionality, design hierarchy, and comments. The HDL Translator, which has been successfully used internally by our engineers for many years is now available for sale. The key benefits include:

Workload Saving
Ease of Maintenance
High Success Rate
Ease of Use
Performance

An example of translated VHDL source code is shown below.

Since the original VHDL code was carefully formatted, the formatting and comments were preserved in the translation. After the translation, the Verilog code looks like this:

Verilog source

Benefits

Workload Saving

Converting several thousand lines of VHDL code into Verilog by hand can take hundreds of engineering man-hours. HDL Translator can do the job in a matter of minutes significantly reducing workload, engineering costs, and time. The cost of the program can be recovered after its single run!

Easy Maintenance

In a complex code comments are crucial to the continuing maintenance of the design. HDL Translator preserves comments and formatting of the original source code.

High Success Rate

A translator that could translate all possible language constructs would be cumbersome and costly. Our HDL Translator takes a practical approach to code conversion: It translates 100% of synthesizeable code and most behavioral code, including the constructs most frequently used in test bench design. The part of source code it cannot translate (usually very small or none) will be commented out, for subsequent manual translation.

Ease of Use

The HDL translator is simple to use. It is implemented as a command line program. As the User Manual states, the translation process is mainly unattended.

Performance

The HDL translator can translate several thousand lines of VHDL code per minute.

Legal

Privacy