USER MANUAL

Preparing the Input VHDL Source Code

Before you begin the conversion, please make sure that:

1. VHDL syntax is correct i.e.  the input source code compiles without errors. To simplify its design, the HDL Translator assumes the syntax of the input file is correct. Run a compiler or a VHDL syntax checker on your input source code.
   
   
2. VHDL code is synthesizeable. The HDL translator will convert 100% of synthesizeable code. It will translate most behavioral code, including the constructs most frequently used in test bench design.
   
   
3. One architecture per entity. If your design contains multiple architectures simply comment out all but one architecture per entity. After conversion you may un-comment another architecture and run the HDL Translator again. This procedure will result in multiple Verilog source codes, each equivalent to a single architecture in VHDL.
   
   
4. Check the case of variable and signal names. VHDL syntax is not case sensitive. Some VHDL source files take advantage of this by using the same variable or signal name in both lowercase and uppercase (or a combination of both) in various sections of the source. This is a bad practice. Verilog is case-sensitive and interprets these as different names. In the worst possible scenario, no error is generated but the user is unaware that some of the wires in the design are now split in two. The solution is to use the -C option to turn off the case sensitivity for names. However, it dramatically increases the execution time, the reason why it is not set as a default.

Running the HDL Translator

Type the following at the command prompt including the path information if needed:


The command line option turns off the case sensitivity of variable/signal names for the reason mentioned in the previous section. Warning: Executes for a long time ! This is the only option supported by the current version (2.0). Hit Enter to start the conversion process. If the design consists of multiple source files, each file must be converted separately. Use a batch (or shell script) file to automate the conversion. The conversion generates two output files:

• filename.v - Verilog source code (result of the conversion)
• filename.out - the conversion status file

Reviewing the Output

Review the output filename.out status file. It indicates conversion errors (if any), and any un-translated constructs in the source code. The un-translated sections are commented out in the Verilog source (file filename.v) and require manual translation. Each entry in the filename.out includes error description and a unique signature to help find the respective un-translated section in the Verilog source file. Review the error descriptions for clues of what went wrong. Sometimes a slight modification of the input VHDL source (and running the translation again) is easier than the post-translation manual editing of the Verilog code.

Verify the Verilog Source

If the conversion generated no errors, verify the resulting Verilog source code by running it through a compiler or a synthesizer.